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參數(shù)資料
| 型號(hào)： | IDT5T905PGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER |
| 中文描述： | 5T SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | IDT5T905PGI |
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INDUSTRIAL TEMPERATURE RANGE
IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
3
PIN DESCRIPTION
Symbol
I/O
A
I
A
/V
REF
I
Type
Description
Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input.
Complementary clock input.
A
/V
REF
is the "complementary" side of A if the input is in differential mode. If operating in single-ended
mode,
A
/V
REF
is connected to GND. For single-ended operation in differential mode,
A
/V
REF
should be set to the desired toggle
voltage for A:
2.5V LVTTL
V
REF
= 1250mV
1.8V LVTTL, eHSTL
V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
Gate control for Qn outputs. When
G
is LOW, these outputs are enabled. When
G
is HIGH, these outputs are asynchronously
disabled to the level designated by GL
(4)
.
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Clock outputs
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in
conjunction with V
DDQ
to set the interface levels.
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, V
DDQ
should be connected to V
DD
.
Power supply return for all power
Adjustable
(1)
Adjustable
(1)
G
I
LVTTL
(5)
GL
Qn
RxS
TxS
I
LVTTL
(5)
Adjustable
(2)
3 Level
(3)
3 Level
(3)
O
I
I
V
DD
V
DDQ
GND
NOTES:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
3. 3 level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to mnimze the possibility of runt
pulses or be able to tolerate themin down streamcircuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
PWR
PWR
PWR
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