參數(shù)資料
型號: IDT5T9050
廠商: Integrated Device Technology, Inc.
英文描述: 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER⑩ JR
中文描述: 2.5V的單數(shù)據(jù)傳輸速率1:5時鐘緩沖器TERABUFFER⑩JR
文件頁數(shù): 2/7頁
文件大?。?/td> 52K
代理商: IDT5T9050
INDUSTRIAL TEMPERATURE RANGE
2
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
TSSOP
TOP VIEW
PIN CONFIGURATION
GL
GND
V
DD
V
DD
GND
GND
GND
G
V
DD
V
DD
Q
1
Q
2
Q
5
GND
GND
Q
3
A
Q
4
V
DD
V
DD
GND
GND
GND
V
DD
V
DD
V
DD
NC
NC
19
15
16
17
18
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
Symbol
V
DD
V
I
V
O
T
STG
T
J
Description
Max
Unit
V
V
V
°C
°C
Power Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Junction Temperature
–0.5 to +3.6
–0.5 to +3.6
–0.5 to V
DD
+0.5
–65 to +165
150
ABSOLUTE MAX IMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
Symbol
C
IN
Parameter
Input Capacitance
Mn
Typ.
6
Max.
Unit
pF
CAPACITANCE
(1)
(T
A
= +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Min.
–40
2.3
Typ.
+25
2.5
Max.
+85
2.7
Unit
°C
V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol
I/O
A
I
G
I
Type
LVTTL
LVTTL
Description
Clock input
Gate control for Qn outputs. When
G
is LOW, these outputs are enabled. When
G
is HIGH, these outputs are asynchronously
disabled to the level designated by GL
(1)
.
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Clock outputs
Power supply for the device core, inputs, and outputs
Power supply return for power
GL
Qn
V
DD
GND
NOTE:
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to mnimze the possibility of runt
pulses or be able to tolerate themin down streamcircuitry.
I
LVTTL
LVTTL
PWR
PWR
O
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