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參數(shù)資料
| 型號： | IDT5T2110NLGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| 封裝： | GREEN, PLASTIC, VFQFP-68 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 207K |
| 代理商： | IDT5T2110NLGI8 |
6
INDUSTRIALTEMPERATURERANGE
IDT5T2110
2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK
DIVIDE SELECTION TABLE
DS [1:0]
Divide-by-n
Permitted Output Divide-by-n connected to FB and FB/VREF2(1)
LL
2
1, 2
LM
3
1
LH
4
1, 2
ML
5
1, 2
M M
1
1, 2, 4
M H
6
1, 2
HL
8
1
HM
10
1
HH
12
1
NOTE:
1. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF[1:0]/VREF[1:0] inputs will be FNOM/N when the parts are configured for
frequency multiplication by using an undivided output for FB and FB/VREF2 and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
EXTERNALDIFFERENTIALFEEDBACK
By providing a dedicated external differential feedback, the IDT5T2110
gives users flexibility with regard to divide selection. The FB and FB/
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]
signals at the phase detector in order to drive the VCO. Phase differ-
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
CONTROL SUMMARY TABLE FOR ALL
OUTPUTS
nF2/FBF2
nF1/FBF1
Output Skew
L
Divide by 2
L
H
ZeroDelay
H
L
Inverted
H
Divide by 4
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