參數(shù)資料
型號(hào)： IDT5T2110BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
中文描述： 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144
封裝： PLASTIC, BGA-144
文件頁數(shù)： 10/23頁
文件大?。?/td> 162K
代理商： IDT5T2110BBI
10
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE FOR eHSTL
(1)
Symbol
Parameter
Test Conditions
Input Characteristics
I
IH
Input HIGH Current
V
DD
= 2.7V
I
IL
Input LOW Current
V
DD
= 2.7V
V
IK
Clamp Diode Voltage
V
DD
= 2.3V, I
IN
= -18mA
V
IN
DC Input Voltage
V
DIF
DC Differential Voltage
(2,8)
V
CM
DC Common Mode Input Voltage
(3,8)
V
IH
DC Input HIGH
(4,5,8)
V
IL
DC Input LOW
(4,6,8)
V
REF
Single-Ended Reference Voltage
(4,8)
Output Characteristics
V
OH
Output HIGH Voltage
I
OH
= -8mA
I
OH
= -100
μ
A
V
OL
Output LOW Voltage
I
OL
= 8mA
I
OL
= 100
μ
A
V
OX
Qn/
Qn
and FB/
FB
Output Crossing Point
Min.
Typ.
(7)
Max
Unit
V
I
= V
DDQ
/GND
V
I
= GND/V
DDQ
—
—
—
- 0.3
0.2
800
—
—
- 0.7
±5
±5
- 1.2
+3.6
—
1000
—
μ
A
V
V
V
900
mV
mV
mV
mV
V
REF
+ 100
—
—
V
REF
- 100
—
900
V
DDQ
- 0.4
V
DDQ
- 0.1
—
—
V
DDQ
/2 - 150
—
—
0.4
0.1
V
V
V
V
V
DDQ
/2
V
DDQ
/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V
DIF
specifies the mnimuminput differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. V
CM
specifies the maximumallowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation, in a differential mode,
REF
[1:0]
/V
REF
[1:0]
is tied to the DC voltage V
REF
[1:0]
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS
(1)
Symbol
Parameter
I
DDQ
Quiescent V
DD
Power Supply Current
(3)
V
DDQ
= Max., REF = LOW,
PD
= HIGH,
nSOE
= LOW,
PLL_EN
= HIGH, DS
[1:0]
= MM nF
[2:1]
= LH,
FBF
[2:1]
= LH, Outputs enabled, All outputs unloaded
I
DDQQ
Quiescent V
DDQ
Power Supply Current
(3)
V
DDQ
= Max., REF = LOW,
PD
= HIGH,
nSOE
= LOW,
PLL_EN
= HIGH, DS
[1:0]
= MM nF
[2:1]
= LH,
FBF
[2:1]
= LH, Outputs enabled, All outputs unloaded
I
DDPD
Power Down Current
V
DD
= Max.,
PD
= LOW,
nSOE
= LOW,
PLL_EN
= HIGH
I
DDD
Dynamc V
DD
Power Supply
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
Current per Output
I
DDDQ
Dynamc V
DDQ
Power Supply
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
Current per Output
I
TOT
Total Power V
DD
Supply Current
(4)
V
DDQ
= 1.8V, F
VCO
= 100MHz, C
L
= 15pF
V
DDQ
= 1.8V, F
VCO
= 250MHz, C
L
= 15pF
I
TOTQ
Total Power V
DDQ
Supply Current
(4)
V
DDQ
= 1.8V, F
VCO
= 100MHz, C
L
= 15pF
V
DDQ
= 1.8V, F
VCO
= 250MHz, C
L
= 15pF
Test Conditions
(2)
Typ.
15
Max
25
Unit
mA
1.7
50
μ
A
0.8
13
3
20
mA
μ
A/MHz
20
30
μ
A/MHz
35
55
50
115
55
85
75
175
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termnation resistors are excluded fromthese measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH
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