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參數(shù)資料
| 型號： | IDT5993A-7Q |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IGBT Module; Continuous Collector Current, Ic:400A; Collector Emitter Saturation Voltage, Vce(sat):2.2V; Power Dissipation, Pd:1130W; Collector Current:400A; Collector Emitter Voltage, Vceo:600V; Mounting Type:; Package/Case:Module RoHS Compliant: Yes |
| 中文描述： | 可編程相偏PLL時鐘驅(qū)動器TURBOCLOCK |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 65K |
| 代理商： | IDT5993A-7Q |
5
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE
IDT5993A-2
Typ.
IDT5993A-5
Typ.
IDT5993A-7
Typ.
Symbol
F
NOM
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
Parameter
VCO Frequency Range
REF Pulse Width HIGH
(1)
REF Pulse Width LOW
(1)
Programmable Skew Time Unit
Zero Output Matched-Pair Skew (xQ
0
, xQ
1
)
(1,2,3)
Zero Output Skew (All Outputs)
(1,4,5)
Output Skew
(Rise-Rise, Fall-Fall, Same Class Outputs)
(1,3)
Output Skew
(Rise-Fall, Divided-Divided)
(1,6)
Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)
(1,6)
Output Skew
(Rise-Fall, Nomnal-Divided)
(1,2)
Device-to-Device Skew
(1,2,7)
REF Input to FB Propagation Delay
(1,9)
Output Duty Cycle Variation from50%
(1)
Output HIGH Time Deviation from50%
(1,10)
Output LOW Time Deviation from50%
(1,11)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(7)
Cycle-to-Cycle Output Jitter
Min.
Max.
See PLL Programmable Skew Range and Resolution Table
—
3
—
—
3
—
See Skew Selection Table for Output Pairs
0.2
—
0.1
0.25
—
0.25
0.5
—
0.6
Min.
Max.
Min.
Max.
Unit
3
3
—
—
—
—
3
3
—
—
—
—
ns
ns
—
—
—
0.05
0.1
0.25
0.25
0.5
0.7
—
—
—
0.1
0.3
0.6
0.25
0.75
1
ns
ns
ns
t
SKEW2
—
0.5
1
—
0.5
1.2
—
0.5
1.5
ns
t
SKEW3
—
0.25
0.5
—
0.5
0.7
—
0.7
1.2
ns
t
SKEW4
—
0.5
0.9
—
0.5
1
—
1.2
1.7
ns
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
—
—
0
0
—
—
1
1
—
—
—
0.75
0.25
1.2
2
1.5
1.2
1.2
0.5
25
200
—
—
0
0
—
—
1
1
—
—
—
1.25
0.5
1.2
2.5
3
1.5
1.5
0.5
25
200
—
—
0
0
—
—
1.5
1.5
—
—
—
1.65
0.7
1.2
3
3.5
2.5
2.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ms
ps
0.25
1.2
—
—
0.15
0.15
—
—
—
0.5
1.2
—
—
0.15
0.15
—
—
—
0.7
1.2
—
—
0.15
0.15
—
—
—
RMS
Peak-to-Peak
NOTES:
1. All timng and jitter tolerances apply for F
NOM
> 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are loaded with the specified
load.
3. t
SKEWPR
is the skew between a pair of outputs (xQ
0
and xQ
1
) when all eight outputs are selected for 0t
U
.
4. t
SKEW0
is the skew between outputs when they are selected for 0t
U
.
5. For IDT5993A-2 t
SKEW0
is measured with C
L
= 0pF; for C
L
= 30pF, t
SKEW0
= 0.35ns Max.
6. There are two classes of outputs: Nomnal (multiple of t
U
delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).
7. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
8. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limts. This parameter is
measured fromthe application of a new signal or frequency at REF or FB until t
PD
is within specified limts.
9. t
PD
is measured with REF input rise and fall times (from0.8V to 2V) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
Maximuminput rise and fall times, 0.8V to 2V
t
PWC
Input clock pulse, HIGH or LOW
D
H
Input duty cycle
R
EF
Reference Clock Input
Description
(1)
Min.
—
3
10
3.75
Max.
10
—
90
100
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limt, t
PWC
limt applies.
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