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參數(shù)資料
| 型號： | IDT5993A-2Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | IGBT Module; Continuous Collector Current, Ic:30A; Collector Emitter Saturation Voltage, Vce(sat):2.8V; Power Dissipation, Pd:150W; Collector Current:30A; Collector Emitter Voltage, Vceo:600V; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 65K |
| 代理商： | IDT5993A-2Q |
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
Supply Voltage to Ground
V
I
DC Input Voltage
MaximumPower Dissipation (T
A
= 85°C)
T
STG
Storage Temperature
Max
Unit
V
V
W
°C
–0.5 to +7
–0.5 to +7
0.66
–65 to +150
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF
1:0
. It is characterized but
not production tested.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
C
IN
Input Capacitance
Typ.
4
Max.
6
Unit
pF
QSOP
TOP VIEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timng relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit t
U
which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
to mnimze the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
PROGRAMMABLE SK EW
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
Type
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control
Summary Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q
0
and 3Q
1
) in a LOW state - 3Q
0
and 3Q
1
may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and GND/
sOE
is HIGH, the nF
[1:0]
pins act as output disable
controls for individual banks when nF
[1:0]
= LL. Set GND/
sOE
LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circiot based on anticipated frequency range. (See PLL Programmable Skew Range.)
Three output banks of two outputs with programmable skew (1Q:3Q), and 4Q output has fixed zero skew outputs.
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
GND/
sOE
(1)
IN
V
CCQ
/PE
IN
nF
[1:0]
FS
nQ
[1:0]
V
CCN
V
CCQ
GND
IN
IN
OUT
PWR
PWR
PWR
NOTE:
1. When TEST = MID and GND/
sOE
= HIGH, PLL remains active with nF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[
1:0
] = LL.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REF
V
CCQ
FS
3F
0
3F
1
4Q
1
4Q
0
GND
3Q
1
3Q
0
V
CCN
FB
GND
TEST
2F
1
2F
0
GND/sOE
1F
1
1F
0
V
CCN
1Q
0
1Q
1
GND
GND
2Q
0
2Q
1
V
CCN
V
CCQ
/PE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5993A-2QI | IGBT Module; Continuous Collector Current, Ic:400A; Collector Emitter Saturation Voltage, Vce(sat):2.2V; Power Dissipation, Pd:960W; Collector Emitter Voltage, Vceo:600V; Package/Case:Module; Transistor Polarity:N Channel RoHS Compliant: Yes |
| IDT5993A-5Q | IGBT Module; Continuous Collector Current, Ic:400A; Collector Emitter Saturation Voltage, Vce(sat):1.7V; Power Dissipation, Pd:890W; Collector Emitter Voltage, Vceo:250V; Package/Case:Module; Transistor Polarity:N Channel RoHS Compliant: Yes |
| IDT5993A-5QI | IGBT Module; Continuous Collector Current, Ic:400A; Collector Emitter Saturation Voltage, Vce(sat):2.8V; Power Dissipation, Pd:1500W; Collector Current:400A; Collector Emitter Voltage, Vceo:600V; Leaded Process Compatible:No RoHS Compliant: No |
| IDT5993A-7Q | IGBT Module; Continuous Collector Current, Ic:400A; Collector Emitter Saturation Voltage, Vce(sat):2.2V; Power Dissipation, Pd:1130W; Collector Current:400A; Collector Emitter Voltage, Vceo:600V; Mounting Type:; Package/Case:Module RoHS Compliant: Yes |
| IDT5993A | Scan Test Devices With 18-Bit Universal Bus Transceiver 64-LQFP -40 to 85 |
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