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參數(shù)資料
| 型號： | IDT59910A-7SOI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. |
| 中文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 52K |
| 代理商： | IDT59910A-7SOI |
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT59910A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
Maximuminput rise and fall times, 0.8V to 2V
t
PWC
Input clock pulse, HIGH or LOW
D
H
Input duty cycle
R
EF
Reference clock input
Description
(1)
Min.
—
3
10
15
Max.
10
—
90
100
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limt, t
PWC
limt applies.
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE
IDT59910A-2
Typ.
—
—
—
—
—
0.1
—
0
0
1
1
—
—
—
IDT59910A-5
Typ.
—
—
—
—
—
0.25
—
0
0
1
1
—
—
—
IDT59910A-7
Typ.
—
—
—
—
—
0.3
—
0.7
1.2
0.15
0.15
—
—
—
Symbol
Parameter
Min.
15
25
40
3
3
—
—
0.25
1.2
0.15
0.15
—
—
—
Max.
35
60
100
—
—
0.25
0.75
0.25
1.2
1.2
1.2
0.5
25
200
Min.
15
25
40
3
3
—
—
0.5
1.2
0.15
0.15
—
—
—
Max.
35
60
100
—
—
0.5
1.25
0.5
1.2
1.5
1.5
0.5
25
200
Min.
15
25
40
3
3
—
—
Max.
35
60
100
—
—
0.75
1.65
0.7
1.2
2.5
2.5
0.5
25
200
Unit
FS = LOW
FS = MED
FS = HIGH
F
REF
REF Frequency Range
MHz
t
RPWH
t
RPWL
t
SKEW0
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
(1,8)
REF Pulse Width LOW
(1,8)
Zero Output Skew (All Outputs)
(1,3,4)
Device-to-Device Skew
(1,2,5)
REF Input to FB Propagation Delay
(1,7)
Output Duty Cycle Variation from50%
(1)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(1,6)
Cycle-to-Cycle Output Jitter
(1)
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
0
0
1.5
1.5
—
—
—
RMS
Peak-to-Peak
NOTES:
1. All timng and jitter tolerances apply for F
NOM
> 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. t
SKEW
is the skew between all outlets. See AC TEST LOADS.
4.
For IDT59910A-2 t
SKEW0
is measured with C
L
= 0pF; for C
L
= 30pF, t
SKEW0
= 0.35ns Max.
5. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
6. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limts. This parameter is
measured fromthe application of a new signal or frequency at REF or FB until t
PD
is within specified limts.
7. t
PD
is measured with REF input rise and fall times (from0.8V to 2V
) of 1ns.
8. Refer to INPUT TIMING REQUIREMENTS for more detail.
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