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參數(shù)資料
| 型號(hào)： | IDT54FCT833AD |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS PARITY BUS TRANSCEIVER |
| 中文描述： | 快速CMOS奇偶總線收發(fā)器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 71K |
| 代理商： | IDT54FCT833AD |
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.21
3
FUNCTION TABLE
(2)
Inputs
Outputs
T
I
Incl Parity
(
∑
of H’s)
NA
NA
NA
NA
OE
T
L
L
L
L
OE
R
H
H
H
H
CLR
CLK
↑
↑
↑
↑
↑
↑
↑
↑
—
R
I
(
∑
or H’s)
H (Odd)
H (Even)
L (Odd)
L (Even)
R
I
NA
NA
NA
NA
T
I
H
H
L
L
Parity
L
H
L
H
ERR
(1)
Function
Transmit data from R Port
to T Port with parity;
receiving path is disabled.
H
H
H
H
H
L
H
L
H
H
H
H
L
L
L
L
H
H
H
H
NA
NA
NA
NA
H (Odd)
H (Even)
L (Odd)
L (Even)
H
H
L
L
NA
NA
NA
NA
NA
NA
NA
NA
H
L
H
L
Receive data from T Port
to R Port with parity test
resulting in flag:
transmitting path is disabled.
—
—
L
—
—
NA
NA
NA
H
Clear the state of error flag
register.
H
H
H
H
H
H
H
H
H
L
H
H
H or L
—
↑
↑
↑
↑
↑
↑
—
—
—
—
—
—
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
H
H
L
Both transmitting and
receiving paths are disabled.
Parity logic defaults to
transmit mode.
H or L (Odd)
H or L (Even)
L
L
L
L
L
L
L
L
H
H
H
H
H (Odd)
H (Even)
L (Odd)
L (Even)
NA
NA
NA
NA
NA
NA
NA
NA
H
H
L
L
H
L
H
L
L
H
L
H
Forced-error checking.
NOTES:
1. Output state assumes HIGH output pre-state.
2. H
=
HIGH
L
=
LOW
↑
=
LOW-to-HIGH transition of clock
*No change to stored Error State
2557 tbl 03
Z
NA =
–
=
High Impedance
Not Applicable
Don’t Care or Irrelevant
Odd =
Even =
I
Odd number of logic one’s
Even number of logic one’s
0, 1, 2, 3, 4, 5, 6, 7
=
=
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| IDT54FCT833ADB | FAST CMOS PARITY BUS TRANSCEIVER |
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| IDT54FCT833AP | FAST CMOS PARITY BUS TRANSCEIVER |
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