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參數(shù)資料
| 型號(hào)： | IDT54FCT377TD |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| 中文描述： | 快速CMOS八路D觸發(fā)器時(shí)鐘使能浮點(diǎn)運(yùn)算 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 111K |
| 代理商： | IDT54FCT377TD |
6.14
6
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
2630 drw 04
2630 drw 05
2630 drw 06
2630 drw 07
2630 drw 08
2630 lnk 08
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| IDT74FCT377TD | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
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| IDT74FCT377TDB | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT54FCT377TE | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
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| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
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