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參數(shù)資料
| 型號： | IDT54FCT377DTDB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| 中文描述： | FCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 111K |
| 代理商： | IDT54FCT377DTDB |
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.14
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2630 tbl 07
2630 tbl 06
IDT54/74FCT377T
FCT54/74FCT377AT
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
t
SU
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min.
(2)
2.0
Max.
13.0
Min.
(2)
2.0
Max.
15.0
Min.
(2)
2.0
Max.
7.2
Min.
(2)
2.0
Max.
8.3
Unit
ns
Propagation Delay
CP to On
Set-Up Time HIGH or LOW
Dn to CP
Hold Time HIGH or LOW
Dn to CP
Set-Up Time HIGH or LOW
CE
to CP
Hold Time HIGH or LOW
CE
to CP
Clock Pulse Width,
HIGH or LOW
2.5
—
3.0
—
2.0
—
2.0
—
ns
t
H
2.0
—
2.5
—
1.5
—
1.5
—
ns
t
SU
4.0
—
4.0
—
3.5
—
3.5
—
ns
t
H
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
W
7.0
—
7.0
—
6.0
—
7.0
—
ns
IDT54/74FCT377CT
FCT54/74FCT377DT
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
t
SU
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min.
(2)
2.0
Max.
5.2
Min.
(2)
2.0
Max.
5.5
Min.
(2)
2.0
Max.
4.4
Min.
(2)
—
Max.
—
Unit
ns
Propagation Delay
CP to On
Set-Up Time HIGH or LOW
Dn to CP
Hold Time HIGH or LOW
Dn to CP
Set-Up Time HIGH or LOW
CE
to CP
Hold Time HIGH or LOW
CE
to CP
Clock Pulse Width,
HIGH or LOW
2.0
—
2.0
—
2.0
—
—
—
ns
t
H
1.5
—
1.5
—
1.0
—
—
—
ns
t
SU
3.5
—
3.5
—
3.0
—
—
—
ns
t
H
1.5
—
1.5
—
0.0
—
—
—
ns
t
W
6.0
—
7.0
—
3.0
—
—
—
ns
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| IDT54FCT377TD | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT74FCT377TD | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT54FCT377TDB | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
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