- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378611 > IDT54FCT377AT (Integrated Device Technology, Inc.) Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 2225; Termination: Sn60 Coated; Body Dimensions: 0.225" x 0.250" x 0.080"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate PDF資料下載
參數(shù)資料
| 型號： | IDT54FCT377AT |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 2225; Termination: Sn60 Coated; Body Dimensions: 0.225" x 0.250" x 0.080"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| 中文描述： | 快速CMOS八路D觸發(fā)器時鐘使能浮點運算 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 111K |
| 代理商： | IDT54FCT377AT |
Integrated Device Technology, Inc.
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (
CE
) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The
CE
input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
IDT54/74FCT377T/AT/CT/DT
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1995
1995 Integrated Device Technology, Inc.
6.14
DSC-4200/3
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Std., A, C and D speed grades
Low input and output leakage
≤
1
μ
A (max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit “l(fā)ive insertion”
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
2630 drw 01
CE
CP
D
CP
Q
D
0
O
0
D
CP
Q
D
1
O
1
D
CP
Q
D
2
O
2
D
CP
Q
D
3
O
3
D
CP
Q
D
4
O
4
D
CP
Q
D
5
O
5
D
CP
Q
D
6
O
6
D
CP
Q
D
7
O
7
FUNCTIONAL BLOCK DIAGRAM
相關PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT377ATD | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT54FCT377ATDB | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT54FCT377ATE | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT54FCT377ATEB | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| IDT54FCT377ATL | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT377DB | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:Flip Flop, Octal, D Type, 20 Pin, Ceramic, DIP |
| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT533DB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。