參數(shù)資料
型號： IDT54FCT257DTEB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通用總線功能
英文描述： FAST CMOS QUAD 2-INPUT MULTIPLEXER
中文描述： FCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDFP16
封裝： CERPACK-16
文件頁數(shù)： 6/7頁
文件大?。?/td> 73K
代理商： IDT54FCT257DTEB
MILITARYANDINDUSTRIALTEMPERATURERANGES
6
IDT54/74FCT257T/AT/CT/DT
FASTCMOSQUAD2-INPUTMULTIPLEXER
Pulse
Generator
R T
D.U.T
.
V CC
VIN
C L
VOUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
相關(guān)PDF資料
PDF描述
IDT54FCT257DTL Ceramic Chip Capacitors / Standard X7R; Capacitance [nom]: 5.6uF; Working Voltage (Vdc)[max]: 16V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R; Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.063"; Container: Bulk; Features: Unmarked
IDT54FCT257DTLB FAST CMOS QUAD 2-INPUT MULTIPLEXER
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