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參數資料
| 型號： | IDT54FCT16841CTPV |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS 20-BIT TRANSPARENT LATCHES |
| 中文描述： | 快速CMOS 20位透明鎖存器 |
| 文件頁數： | 7/9頁 |
| 文件大?。?/td> | 135K |
| 代理商： | IDT54FCT16841CTPV |
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.18
7
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
2556 tbl 10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
FCT16841CT/162841CT
FCT16841ET/162841ET
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
xDx to xQx
(LE = HIGH)
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(5)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(5)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(5)
R
L
= 500
C
L
= 5pF
(5)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 50pF
R
L
= 500
1.5
5.5
1.5
6.3
1.5
3.4
—
—
ns
1.5
13.0
1.5
15.0
1.5
7.5
—
—
t
PLH
t
PHL
Propagation Delay
xLE to xQx
1.5
6.4
1.5
6.8
1.5
3.7
—
—
ns
1.5
15.0
1.5
16.0
1.5
7.5
—
—
t
PZH
t
PZL
Output Enable Time
x
OE
to xQx
1.5
6.5
1.5
7.3
1.5
4.4
—
—
ns
1.5
12.0
1.5
13.0
1.5
9.0
—
—
t
PHZ
t
PLZ
Output Disable Time
x
OE
to xQx
1.5
5.7
1.5
6.0
1.5
3.6
—
—
ns
1.5
6.0
1.5
6.3
1.5
3.6
—
—
t
SU
Set-Up Time HIGH or LOW,
xDx to xLE
Hold Time HIGH or LOW,
xDx to xLE
xLE Pulse Width HIGH
2.5
—
2.5
—
1.0
—
—
—
ns
t
H
2.5
—
2.5
—
1.0
—
—
—
ns
t
W
4.0
(4)
—
4.0
(4)
—
3.0
(4)
—
—
—
ns
t
SK
(o)
Output skew
(3)
—
0.5
—
0.5
—
0.5
—
—
ns
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