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參數(shù)資料
| 型號： | IDT54FCT16646CTE |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS (3-STATE) |
| 中文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封裝： | 0.025 INCH PITCH, CERPACK-56 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 177K |
| 代理商： | IDT54FCT16646CTE |
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.13
7
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
2540 tbl 09
2540 tbl10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
FCT16646T/162646T
FCT16646AT/162646AT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
Propagation Delay
Bus to Bus
Output Enable Time
xDIR or x
OE
to Bus
Output Disable Time
xDIR or x
OE
to Bus
Propagation Delay
Clock to Bus
Propagation Delay
xSBA or xSAB to Bus
Set-up Time HIGH or
LOW Bus to Clock
Hold Time HIGH or
LOW Bus to Clock
Clock Pulse Width
HIGH or LOW
Output Skew
(3)
C
L
= 50pF
R
L
= 500
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
ns
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
ns
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
ns
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
ns
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
ns
4.0
—
4.5
—
2.0
—
2.0
—
ns
t
H
2.0
—
2.0
—
1.5
—
1.5
—
ns
t
W
6.0
—
6.0
—
5.0
—
5.0
—
ns
t
SK
(o)
—
0.5
—
0.5
—
0.5
—
0.5
ns
FCT16646CT/162646CT
FCT16646ET/162646ET
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
Propagation Delay
Bus to Bus
Output Enable Time
xDIR or x
OE
to Bus
Output Disable Time
xDIR or x
OE
to Bus
Propagation Delay
Clock to Bus
Propagation Delay
xSBA or xSAB to Bus
Set-up Time HIGH or
LOW Bus to Clock
Hold Time HIGH or
LOW Bus to Clock
Clock Pulse Width
HIGH or LOW
Output Skew
(3)
C
L
= 50pF
R
L
= 500
1.5
5.4
1.5
6.0
1.5
3.8
—
—
ns
1.5
7.8
1.5
8.9
1.5
4.8
—
—
ns
1.5
6.3
1.5
7.7
1.5
4.0
—
—
ns
1.5
5.7
1.5
6.3
1.5
3.8
—
—
ns
1.5
6.2
1.5
7.0
1.5
4.2
—
—
ns
2.0
—
2.0
—
2.0
—
—
—
ns
t
H
1.5
—
1.5
—
0.0
—
—
—
ns
t
W
5.0
—
5.0
—
3.0
(4)
—
—
—
ns
t
SK
(o)
—
0.5
—
0.5
—
0.5
—
—
ns
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