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參數(shù)資料
| 型號： | IDT54FCT162H952ETEB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封裝： | 0.635 MM PITCH, CERPACK-56 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 126K |
| 代理商： | IDT54FCT162H952ETEB |
2
MILITARYANDCOMMERCIALTEMPERATURERANGES
IDT54/74FCT162H952AT/BT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
5v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
1
B1
1
B2
GND
1
B3
1
B4
V CC
1
B5
1
B6
1
O EBA
1
B7
1
B8
2
B1
2
B2
GND
2
B3
2
B4
V CC
2
B5
GND
1
C LKBA
2
B7
2
B6
2
B8
GND
2
C LKBA
2
O EBA
1
CLKAB
GND
1
A 1
1
A 2
VCC
1
A 3
1
A 4
GND
1
A 5
1
A 6
1
A 7
1
A 8
GND
2
A 1
2
A 2
VCC
2
A 3
2
A 5
2
A 4
2
A 7
GND
2
A 8
2
CLKAB
2
A 6
1
O EAB
1
C EAB
2
O EAB
2
C EAB
2
C EBA
1
C EBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SO 56-1
SO 56-2
SO 56-3
E56-1
29
30
31
32
25
26
27
28
FUNCTION TABLE(1,3)
Inputs
Outputs
xCEAB
xCLKAB
xOEAB
xAx
xBx
HXL
X
B(2)
XL
L
X
B
(2)
L
↑
LL
L
↑
LH
H
XX
H
X
Z
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses x
CEBA,
xCLKBA, and x
OEBA.
2. Level of B before the indicated steady-state input conditions were
established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
PIN DESCRIPTION
Pin Names
Description
xOEAB
A-to-B Output Enable Input (Active LOW)
xOEBA
B-to-A Output Enable Input (Active LOW)
xCEAB
A-to-B Clock Enable Input (Active LOW)
xCEBA
B-to-A Clock Enable Input (Active LOW)
xCLKAB
A-to-B Clock Input
xCLKBA
B-to-A Clock Input
x A x
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
x B x
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
NOTE:
1. These pins have “Bus Hold”. All other pins are standard inputs, outputs
or I/Os.
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