參數(shù)資料
型號(hào): IDT54FCT162373TEB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48
封裝: CERPACK-48
文件頁數(shù): 5/7頁
文件大?。?/td> 113K
代理商: IDT54FCT162373TEB
5
IDT54/74FCT162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162373T
FCT162373AT
Ind.
Mil.
Ind.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
xDx to xOx
CL = 50pF
RL = 500
1.5
8
1.5
8.5
1.5
5.2
1.5
5.6
ns
tPLH
tPHL
Propagation Delay
xLE to xOx
2
13
2
15
28.529.8
ns
tPZH
tPZL
Output Enable Time
1.5
12
1.5
13.5
1.5
6.5
1.5
7.5
ns
tPHZ
tPLZ
Output Disable Time
1.5
7.5
1.5
10
1.5
5.5
1.5
6.5
ns
tSU
Set-up Time HIGH or LOW, xDx to xLE
2
2
2
2
ns
tH
Hold Time HIGH or LOW, xDx to xLE
1.5
1.5
1.5
1.5
ns
tW
xLE Pulse Width HIGH
6
6
5
6
ns
tSK(o)
Output Skew(3)
0.5
0.5
0.5
0.5
ns
FCT162373CT
FCT162373ET
Ind.
Mil.
Ind.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
xDx to xOx
CL = 50pF
RL = 500
1.5
4.2
1.5
5.1
1.5
3.4
ns
tPLH
tPHL
Propagation Delay
xLE to xOx
2
5.5
2
8
1.5
3.7
ns
tPZH
tPZL
Output Enable Time
1.5
5.5
1.5
6.3
1.5
4.4
ns
tPHZ
tPLZ
Output Disable Time
1.5
5
1.5
5.9
1.5
3.6
ns
tSU
Set-up Time HIGH or LOW, xDx to xLE
2
2
1
ns
tH
Hold Time HIGH or LOW, xDx to xLE
1.5
1.5
1
ns
tW
xLE Pulse Width HIGH
5
6
3(4)
——
ns
tSK(o)
Output Skew(3)
0.5
0.5
0.5
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
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