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參數(shù)資料
| 型號： | IDT54823BDSOB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| 中文描述： | 高性能CMOS總線接口寄存器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 89K |
| 代理商： | IDT54823BDSOB |
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
PIN CONFIGURATION
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC
TOP VIEW
LCC
TOP VIEW
2
3
1
20
19
18
15
16
9
10
D
6
D
7
D
2
D
5
D
3
D
4
D
8
23
22
24
21
17
5
6
7
4
8
D
0
V
CC
CP
OE
13
14
11
12
D
1
GND
CLR
Y
6
Y
7
Y
2
Y
5
Y
3
Y
4
Y
8
Y
0
Y
1
EN
15
16
N
12
13
14
G
D
8
17
18
C
E
Y
8
N
V
C
O
D
1
D
0
Y
0
Y
1
Y
3
Y
4
NC
Y
5
5
6
8
7
9
10
11
1
28
4
3
2
27
26
25
24
22
23
21
20
19
D
5
D
6
NC
D
3
D
4
D
2
D
7
INDEX
C
Y
2
Y
7
Y
6
LOGIC SY MBOL
CP
D
OE
Q
D
CP
EN
Y
9
9
EN
CLR
CLR
Symbol
V
TERM
(2)
Rating
Termnal Voltage
with Respect to GND
Termnal Voltage
with Respect to GND
Operating Temperature
Temperature under BIAS
Storage Temperature
Power Dissipation
DC Output Current
Commercial
–0.5 to +7
Military
–0.5 to +7
Unit
V
V
TERM
(3)
–0.5 to V
CC
–0.5 to V
CC
V
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
ABSOLUTE MAX IMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability. No termnal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc termnals only.
3. Output and I/O termnals only.
Pin Name
Dx
CLR
I/O
I
I
Description
D flip-flop data inputs
For both inverting and non-inverting registers, when
the clear input is LOW and
OE
is LOW, the Q
x
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Register 3-state outputs
Clock Enable. When the clock enable is LOW, data
on the D
I
input is transferred to the Q
I
output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the Q
I
outputs do not change state,
regardless of the data or clock input transitions.
Output Control. When the
OE
input is HIGH, the Yx
outputs are in the high impedance state. When the
OE
input is LOW, the TRUE register data is present at the
Yx
outputs.
CP
I
Yx
EN
O
I
OE
I
PIN DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT54823BLSO | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
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