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參數(shù)資料
| 型號(hào)： | IDT43ALVCH16823PA |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| 中文描述： | 3.3V的CMOS 18位總線接口觸發(fā)器具有三態(tài)輸出和總線狀態(tài)保持 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 79K |
| 代理商： | IDT43ALVCH16823PA |
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
V
OH
V
T
0V
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
TIMING
INPUT
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
t
REM
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OL
V
OH
V
HZ
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
ALVC Link
TEST CIRCUITS AND WAV EFORMS
TEST CONDITIONS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termnation resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagramshown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc
/ 2
150
150
30
Unit
V
V
V
mV
mV
pF
6
2.7
1.5
300
300
50
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT43LVC162374APA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD |
| IDT43LVC162374APF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD |
| IDT43LVC162374APV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD |
| IDT44ALVCH16823PA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT44LVC162374APA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD |
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