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參數(shù)資料
| 型號(hào)： | IDT29FCT52CSOB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| 中文描述： | 快速CMOS八進(jìn)制注冊(cè)收發(fā)器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 62K |
| 代理商： | IDT29FCT52CSOB |
7.1
2
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Name
A
0-7
B
0-7
CPA
I/O
I/O
I/O
I
Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
Clock for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal.
Clock Enable for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH
transition of the CPA signal. When
CEA
is HIGH, the A Register holds its contents, regardless of CPA signal
transitions.
Output Enable for the A Register. When
OEB
is LOW, the A Register outputs are enabled onto the B
0-7
lines. When
OEB
is HIGH, the B
0-7
outputs are in the high-impedance state.
Clock for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal.
Clock Enable for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH
transition of the CPB signal. When
CEB
is HIGH, the B Register holds its contents, regardless of CPB signal
transitions.
Output Enable for the B Register. When
OEA
is LOW, the B Register outputs are enabled onto the A
0-7
lines. When
OEA
is HIGH, the A
0-7
outputs are in the high-impedance state.
CEA
I
OEB
I
CPB
I
CEB
I
OEA
I
2533 tbl 01
PIN CONFIGURATIONS
DIP/CERPACK/SOIC
TOP VIEW
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A
7
P24-1,
D24-1,
E24-1
&
SO24-2
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CEB
CEA
CPB
CPA
OEA
B
6
B
5
B
4
B
3
B
2
B
1
B
B
7
0
OEB
REGISTER FUNCTION TABLE
(1)
(Applies to A or B Register)
Inputs
D
CP
X
X
L
↑
H
↑
Internal
Q
NC
L
H
CE
H
L
L
Function
Hold Data
Load Data
2533 tbl 02
OUTPUT CONTROL
(1)
Internal
OE
Y-Outputs
Q
X
L
H
52
Z
L
H
53
Z
H
L
Function
Disable Outputs
Enable Outputs
H
L
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
2533 tbl 03
5
6
7
8
9
10
11
L28-1
25
24
23
22
21
20
19
INDEX
B
4
B
3
B
2
NC
B
1
B
0
OEB
N
V
A
7
A
6
B
5
B
6
B
7
G
C
C
N
C
C
O
NC
A
2
A
1
A
0
A
5
A
4
A
3
12 13 14 15 16 17 18
4
3
2
1
28 27 26
LCC
TOP VIEW
2533 drw 02
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IDT29FCT52CT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
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| IDT29FCT52CTPY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-bit Bus Transceiver |
| IDT29FCT52CTQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-bit Bus Transceiver |
| IDT29FCT52CTSO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 8-bit Bus Transceiver |
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