參數(shù)資料
型號: IDT29FCT52CDB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通用總線功能
英文描述: FAST CMOS OCTAL REGISTERED TRANSCEIVERS
中文描述: FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24
封裝: 0.300 INCH, CERDIP-24
文件頁數(shù): 6/7頁
文件大?。?/td> 62K
代理商: IDT29FCT52CDB
7.1
6
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
Pulse
Generator
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
t
SU
t
H
t
REM
H
t
SU
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OL
V
OH
t
PLH
t
PHL
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
3V
1.5V
0V
t
PLH
t
PHL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
t
NOTES
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0 MHz; Z
O
50
; t
F
2.5ns;
t
R
2.5ns.
2533 drw 04
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2533 tbl 09
相關PDF資料
PDF描述
IDT29FCT53ASO FAST CMOS OCTAL REGISTERED TRANSCEIVERS
IDT29FCT53B FAST CMOS OCTAL REGISTERED TRANSCEIVERS
IDT29FCT53BD FAST CMOS OCTAL REGISTERED TRANSCEIVERS
IDT29FCT53BDB FAST CMOS OCTAL REGISTERED TRANSCEIVERS
IDT29FCT53BE FAST CMOS OCTAL REGISTERED TRANSCEIVERS
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