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參數(shù)資料
| 型號： | IDT29FCT521DT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | MULTILEVEL PIPELINE REGISTERS |
| 中文描述： | 8-BIT, DSP-PIPELINE REGISTER, PDSO24 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 93K |
| 代理商： | IDT29FCT521DT |
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
DESCRIPTION:
The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/
BT/CT/DT each contain four 8-bit positive edge-triggered
registers. These may be operated as a dual 2-level or as a
single 4-level pipeline. A single 8-bit input is provided and any
of the four registers is available at the 8-bit, 3-state output.
These devices differ only in the way data is loaded into and
between the registers in 2-level operation. The difference is
illustrated in Figure 1. In the IDT29FCT520AT/BT/CT/DT
when data is entered into the first level (I = 2 or I = 1), the
existing data in the first level is moved to the second level. In
the IDT29FCT521AT/BT/CT/DT, these instructions simply
cause the data in the first level to be overwritten. Transfer of
data to the second level is achieved using the 4-level shift
instruction (I = 0). This transfer also causes the first level to
change. In either part I=3 is for hold.
FUNCTIONAL BLOCK DIAGRAM
2619 drw 01
REGISTER
CONTROL
2
1
I ,I
1
0
CLK
OCTAL REG. A1
OCTAL REG. A2
OCTAL REG. B1
OCTAL REG. B2
MUX
MUX
2
S ,S
1
0
8
Y -Y
7
0
OE
8
D -D
7
0
MULTILEVEL
PIPELINE REGISTERS
IDT29FCT520AT/BT/CT/DT
IDT29FCT521AT/BT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1994
1994 Integrated Device Technology, Inc.
DSC-4215/4
1
FEATURES:
A, B, C and D speed grades
Low input and output leakage
≤
1
μ
A (max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
6.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT29FCT520BSOB | MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520ASOB | MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520CSOB | MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520CEB | MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520CPB | MULTILEVEL PIPELINE REGISTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT29FCT521DTP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| IDT29FCT521DTPY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| IDT29FCT521DTSO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| IDT29FCT52A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| IDT29FCT52AD | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
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