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參數(shù)資料
| 型號(hào)： | ID82C82 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 0K |
| 描述： | IC DRIVER BUS OCT LATCHING 20DIP |
| 標(biāo)準(zhǔn)包裝： | 190 |
| 類型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-CDIP |
| 包裝： | 管件 |
275
Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unre-
lated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between VCC and GND when
the signal is at or near the input switching threshold. Addition-
ally, if the driving signal becomes high impedance (“float” con-
dition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
The Intersil 82C8X Series of bus drivers eliminates these con-
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE = logic one for 82C86H/87H). These gated inputs dis-
connect the input circuitry from the VCC and ground power
supply pins by turning off the upper P-channel and lower N-
channel (see Figures 1, 2). No new current flow from VCC to
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the max-
imum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
DIO
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
STB
DQ
CLK
FIGURE 16. 82C82/83H
FIGURE 17. 82C86H/87H GATED INPUTS
P
N
STB
DATA IN
INTERNAL
DATA
VCC
P
N
OE
DATA IN
INTERNAL
DATA
VCC
P
N
VCC
82C82
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ID82C82/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Non-Inverting Buffer/Driver |
| ID82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| ID82C83H/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Inverting Buffer/Driver |
| ID82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| ID82C84A/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
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