- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383098 > ID82C50A (HARRIS SEMICONDUCTOR) CMOS Asynchronous Communications Element PDF資料下載
參數(shù)資料
| 型號(hào)： | ID82C50A |
| 廠(chǎng)商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | CMOS Asynchronous Communications Element |
| 中文描述： | 1 CHANNEL(S), 625K bps, SERIAL COMM CONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 11/21頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | ID82C50A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
11
TRANSMITTER HOLDING REGISTER (THR)
The Transmitter Holding Register (THR) holds parallel data
from the data bus (D0-D7) until the Transmitter Shift Register
is empty and ready to accept a new character for transmis-
sion. The transmitter and receiver word length and number
of stop bits are the same. If the character is less than eight
bits, unused bits at the microprocessor data bus are ignored
by the transmitter.
Data Bit 0 (THR(0)) is the first serial data bit transmitted. The
THRE flag (LSR(5)) reflect the status of the THR. The TEMT
flag (LSR(6)) indicates if both the THR and TSR are empty.
THR Bits 0 thru 7
THR (0)
THR (1)
THR (2)
THR (3)
THR (4)
THR (5)
THR (6)
THR (7)
SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write register has no effect on the 82C50A.
It is intended as a scratchpad register to be used by the pro-
grammer to hold data temporarily.
SCR Bits 0 thru 7
SCR (0)
SCR (1)
SCR (2)
SCR (3)
SOR (4)
SCR (5)
SOR (6)
SCR (7)
Interrupt Structure
INTERRUPT IDENTIFICATION REGISTER (IIR)
The 82C50A has interrupt capability for interfacing to current
microprocessors. In order to minimize software overhead
during data character transfers, the 82C50A prioritizes
interrupts into four levels. The four levels of interrupt condi-
tions are as follows:
1. Receiver Line Status (Priority 1)
2. Received Data Ready (Priority 2)
3. Transmitter Holding Register Empty (Priority 3)
4. Modem Status (Priority 4).
Information indicating that a prioritized interrupt is pending
and the type of interrupt is stored in the Interrupt Identifica-
tion Register (IIR). When addressed during chip select time,
the lIR indicates the highest priority interrupt pending. No
other interrupts are acknowledged until the interrupt is ser-
viced by the CPU. The contents of the lIR are indicated in
Table 2 and are described below.
IIR(0):
IIR(0) can be used in either a hardwired prioritized or
polled environment to indicate whether an interrupt is pend-
ing. When IIR(0) is low, an interrupt is pending, and the lIR
contents may be used as a pointer to the appropriate inter-
rupt service routine. When lIR(0) is high, no interrupt is
pending.
IlR(1) and IIR(2):
llR(1) and IlR(2) are used to identify the
highest priority interrupt pending as indicated in Table 2.
lIR(3) - IIR(7):
These five bits of the lIR are logic 0.
INTERRUPT ENABLE REGISTER (IER)
The Interrupt Enable Register (IER) is a Write register used
to independently enable the four 82C50A interrupts which
activate the interrupt (lNTRPT) output. All interrupts are dis-
abled by resetting IER(0) - IER(3) of the Interrupt Enable
Register. Interrupts are enabled by setting the appropriate
bits of the IER high. Disabling the interrupt system inhibits
the Interrupt Identification Register and the active (high)
INTRPT output. All other system functions operate in their
normal manner, including the setting of the Line Status and
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
TABLE 2. INTERRUPT IDENTIFICATION REGISTER
INTERRUPT IDENTIFICATION
INTERRUPT SET AND RESET FUNCTIONS
BIT 2
BIT 1
BIT 0
PRIORITY
LEVEL
INTERRUPT
FLAG
INTERRUPT
SOURCE
INTERRUPT
RESET CONTROL
X
X
1
None
None
1
1
0
First
Receiver Line
Status
OE, PE, FE, or
BI
LSR Read
1
0
0
Second
Received Data
Available
Receiver Data
Available
RBR Read
0
1
0
Third
THRE
THRE
IIR Read if THRE is the
Interrupt Source or
THR Write
0
0
0
Fourth
Modem Status
CTS, DSR, RI,
DCD
MSR Read
NOTE: X = Not Defined, May Be 0 or 1
82C50A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ID82C52 | CMOS Serial Controller Interface |
| ID82C54 | CMOS Programmable Interval Timer |
| ID82C54-10 | CMOS Programmable Interval Timer |
| ID82C54-12 | CMOS Programmable Interval Timer |
| ID82C59A | CMOS Priority Interrupt Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ID82C50A-5 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Asynchronous Communications Element |
| ID82C52 | 功能描述:UART 接口集成電路 PERIPH UART/BRG 5V 16MHZ 28CDIP IND RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ID82C52/+ | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:UART |
| ID82C54 | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 PERIPH PRG-CNTR 5V 8MHZ 24CDIP IND RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| ID82C54/+ | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog Timer Circuit |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。