參數(shù)資料
型號(hào)： ID82C237
廠商： INTERSIL CORP
元件分類： DMA控制器
英文描述： CMOS High Performance Programmable DMA Controller
中文描述： 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CDIP40
封裝： SIDE BRAZED, DIP-40
文件頁(yè)數(shù)： 15/25頁(yè)
文件大小： 158K
代理商： ID82C237
4-162
82C237
Application Information
Figure 7 shows an application for a DMA system utilizing the
82C237 DMA controller and the 80C88 Microprocessor. In
this application, the 82C237 DMA controller is used to
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.
Components
The system clock is generated by the 82C84A clock driver
and is inverted to meet the clock high and low times required
by the 82C237 DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The most signifi-
cant bits of the address are output on the address/data bus.
Therefore, the 82C82 octal latch is used to demultiplex the
address. Hold Acknowledge (HLDA) and Address Enable
(AEN) are “ORed” together to insure that the DMA controller
does not have bus contention with the microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowl-
edge signal is returned to the DMA controller from the
80C88 processor. After the Hold Acknowledge has been
received, addresses and control signals are generated by
the DMA controller to accomplish the DMA transfers. Data is
transferred directly from the I/O device to memory (or vice
versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-memory or memory-to-I/O data
transfers.
FIGURE 7. APPLICATION FOR DMA SYSTEM
MEMR
MEMW
IOR
IOW
MEMCS
MEMR
MEMW
MEMORY
47K
V
CC
ADDRESS BUS
DATA BUS
V
CC
DATA BUS
80C88
WR
RD
M/IO
HRQ
HLDA
AX
ALE
AD0
AD7
MN/MX
CLK
82C84A
OR
82C85
HLDA
MEMCS
STB
82C82
OE
DECODER
ADDRESS BUS
STB
82C82
OE
A0-7
DB0-7
CS
ADSTB
CLK
EOP
HLDA
IOR
IOW
MEMR
MEMW
HRQ
DREQ0
DACK
AEN
82C237
IOR
IOW
V
CC
CS
DREQ
I/O
DEVICE
NOTE: The address lines need pull-up resistors.
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