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參數(shù)資料
| 型號： | ICX202 |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| 中文描述： | 時序發(fā)生器和幀讀出CCD圖像傳感器信號處理器 |
| 文件頁數(shù)： | 48/49頁 |
| 文件大?。?/td> | 403K |
| 代理商： | ICX202 |
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48
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CXD3410GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block V
DD1
, V
DD2
, V
DD3
, V
DD4
and V
DD5
pin and CCD signal processor
block DV
DD1
, DV
DD2
, AV
DD1
, AV
DD2
, AV
DD3
, AV
DD4
and AV
DD5
pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block V
DD1
, V
DD2
, V
DD3
, V
DD4
and V
DD5
pins from the CCD signal processor
block DV
DD1
, DV
DD2
, AV
DD1
, AV
DD2
, AV
DD3
, AV
DD4
and AV
DD5
pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DV
DD1
. Separating this
pin from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block V
DD4
pin supply voltage 3 V
DD
c and the CCD
signal processor block DV
DD1
, DV
DD2
, AV
DD1
, AV
DD2
, AV
DD3
, AV
DD4
and AV
DD5
pin supply voltages 1 V
DD
e,
2 V
DD
f and 3 V
DD
g should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block V
SS1
, V
SS2
, V
SS3
, V
SS4
,
V
SS5
, V
SS6
and VM and the CCD signal processor block DV
SS1
, DV
SS2
, DV
SS3
, AV
SS1
, AV
SS2
, AV
SS3
, AV
SS4
,
AV
SS5
and AV
SS6
should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
t1
t2
15.0V
0V
–
7.5V
20%
20%
t2
≥
t1
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