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參數(shù)資料
| 型號： | ICX039BLB |
| 廠商： | Sony Corporation |
| 英文描述： | CIR 55C 55#16 PIN PLUG |
| 中文描述： | 對角線毫米（類型1 / 2）CCD圖像傳感器的無線電咨詢委員會黑與白錄相機(jī) |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 218K |
| 代理商： | ICX039BLB |
– 5 –
ICX039DLA
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
φ
V
| V
VH1
– V
VH2
|
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
φ
H
V
HL
V
RGL
V
φ
RG
V
RGLH
– V
RGLL
V
φ
SUB
14.55
–0.05
–0.2
–9.6
8.3
–0.25
–0.25
4.75
–0.05
4.5
23.0
15.0
0
0
–9.0
9.0
5.0
0
1
5.0
24.0
15.45
0.05
0.05
–8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
φ
V
= V
VH
n – V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
1
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max. Unit
Waveform
diagram
Remarks
Item
Symbol
Min.
Typ.
Max. Unit
Waveform
diagram
Remarks
1
Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Reset gate clock
voltage
V
RGL
V
φ
RG
–0.2
8.5
0
9.0
0.2
9.5
V
Vp-p
4
4
Clock Voltage Conditions
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相關(guān)代理商/技術(shù)參數(shù) |
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