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參數(shù)資料
| 型號(hào)： | ICSSSTVA16859CKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
| 封裝： | LEAD FREE,MLF-56 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 183K |
| 代理商： | ICSSSTVA16859CKLF |
8
ICSSSTVF16859B
1019B—03/15/05
Notes:
1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
Test Point
CL = 30 pF
(see Note 1)
From Output
Under Test
Load Circuit
500
LVCMOS
RESET#
Input
LVCMOS
RESET#
Input
V
DDQ
/2
V
DDQ
/2
tinact
tact
I
(see note 2)
DD
IDDH
IDDL
10%
90%
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
Figure 1 - Parameter Measurement Information (V
DDQ = 2.5V ±0.2V)
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
VDDQ
0V
t
w
t
S
t
h
VIH
VOH
VTT
VOH
VIH
VIL
VOL
VI(pp)
VIL
VREF
VICR
tPHL
V/2
DD
VICR
Input
Timing
Input
Timing
Input
Output
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