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參數(shù)資料
| 型號： | ICSSSTVA16859CK |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
| 封裝： | LEAD FREE,MLF-56 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 183K |
| 代理商： | ICSSSTVA16859CK |
7
ICSSSTVF16859B
1019B—03/15/05
Timing Requirements
1
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
270
MHz
tSL
Output slew rate
1
4
V/ns
Setup time, fast slew rate
2 & 4
0.4
ns
Setup time, slow slew rate
3 & 4
0.6
ns
Hold time, fast slew rate
2 & 4
0.4
ns
Hold time, slow slew rate
3 & 4
0.5
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of ≥ 1V/ns.
4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.
SYMBOL
tS
Th
Notes:
3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.
VDDQ = 2.5V ± 0.2V
UNITS
PARAMETERS
Data before CLK↑ , CLK#↓
Data after CLK↑ , CLK#↓
Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
MIN
TYP
MAX
fmax
210
MHz
CLK, CLK# (TSSOP)
Q
1.6
2.1
2.6
ns
CLK, CLK# (VFQFN[MLF2])
Q
1.6
2.1
2.6
ns
tphl
RESET#
Q
3.5
ns
SYMBOL
VDD = 2.5V ±0.2V
UNITS
From
(Input)
To
(Output)
tPD
Switching Characteristics - DDRI-400 (PC3200)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
MIN
TYP
MAX
fmax
210
MHz
tPD
Q1.1
2.2
ns
tPDSS
Q2.48
ns
tphl
RESET#
Q
3.5
ns
SYMBOL
VDD = 2.6V ±0.1V
UNITS
From
(Input)
To
(Output)
(VFQFN[MLF2])
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTVF16859 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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