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參數(shù)資料
| 型號： | ICSSSTVA16859CGLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| 封裝： | 0.240 INCH, LEAD FREE, MO-153, TSSOP-64 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 183K |
| 代理商： | ICSSSTVA16859CGLF-T |
6
ICSSSTVF16859B
1019B—03/15/05
DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
VDDQ
MIN
TYP
MAX
UNITS
VIK
II = -18mA
2.5V
-1.2
IOH = -100A
2.5V-2.7V
VDDQ -
0.2
IOH = -8mA
2.7V
1.95
IOL = 100A
2.5V-2.7V
0.2
IOL = 8mA
2.5V
0.35
II
All Inputs
VI = VDD or GND
2.7V
±5
A
Standby (Static)
RESET# = GND
0.01
A
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
TBD
mA
Dynamic operating
(clock only)
RESET# = VDD,
VI
= VIH(AC) or VIL(AC), CLK
and CLK# switching 50%
duty cycle.
TBD
/clock MHz
Dynamic Operating
(per each data input)
RESET# = VDD,
VI
= VIH(AC) or VIL (AC), CLK
and CLK# switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle
TBD
A/ clock
MHz/data
rOH
Output High
2.5V-2.7V
7
13.5
20
rOL
Output Low
2.5V-2.7V
7
13
20
rO(D)
[rOH - rOL] each
separate bit
2.6V
4
Data Inputs
2.5
3.5
CLK and CLK#
2.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
Ci
IOL = 16mA
IO = 20mA, TA = 25° C
VOH
VOL
IDD
IDDD
IO = 0
CONDITIONS
2.7V
2.6V
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
pF
IOH = -16mA
V
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|---|---|
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