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參數(shù)資料
| 型號(hào)： | ICSLV218RILFT |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 218 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, MO-153, SSOP-28 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 141K |
| 代理商： | ICSLV218RILFT |
ICSLV218
MDS LV218 A
1
Revision 083105
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
Dual 1-to-8 Low Voltage Clock Buffer/Translator
PRELIMINARY INFORMATION
Description
The ICSLV218 is a high-speed clock buffer consisting
of two independent single-input to eight-output
low-skew, non-inverting clock drivers.
The ICSLV218 has three independent supply rails: The
input supply rail, VDDIN, operates from a fixed 2.5 V
supply, while the output supply rails, VDDA and VDDB,
operate from 2.5 V-3.3 V and 1.8 V-2.5 V supplies
respectively. This configuration, combined with 3.3 V
tolerance on the INA and INB inputs, allows for many
different possibilities of up and/or down voltage
translation.
Features
Dual 1:8 clock drivers
Pin-compatible with MK74CB218
Independent supply rails on input and output banks
for voltage translation
3.3 V input tolerance
Low skew outputs within same bank (150 ps)
Output Enable tri-states both banks of eight
Clock speeds up to 200 MHz
Industrial temperature range (-40 to 85°C)
28-pin SSOP (150 mil body) Pb (lead) free package
Block Diagram
VDDIN
(2.5V)
GND
OE (all outputs)
QB5
QB7
QB4
QB6
QB1
QB3
QB0
QB2
VDDA
(2.5V-3.3V)
VDDB
(1.8V-2.5V)
INB (3.3V tolerant)
QA5
QA7
QA4
QA6
QA1
QA3
QA0
QA2
(3.3V tolerant) INB
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