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參數(shù)資料
| 型號： | ICS95V860 |
| 英文描述： | 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
| 中文描述： | 2.5伏的DDR /零延遲扇出緩沖器（100MHz的- 225MHz?1800MHz的） |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 95K |
| 代理商： | ICS95V860 |
4
ICS95V860
0675D—01/07/04
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 3.6V
Logic Inputs (except SDA, SCL) . . . . . . . . . GND –0.5 V to V
DD
+ 0.5 V
Logic Inputs (SDA, SCL) . . . . . . . . . . . . . . . GND –0.5 V to V
DDI2C
+ 0.6 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
The
ICS95V860
is able to track Spread Spectrum Clock (SSC) for reduced EMI.
The
ICS95V860
is an I
2
C slave/receiver that supports standard and "fast" mode. The
ICS95V860
I
2
C interface is
compliant to "The I2C-Bus Specification", version 2.1 January 2000 Philips Semiconductors, except that I2C_SDA
and I2C_SCL are not 5.0V tolerant, but have a maximum input voltage of 4.2V or V
DDI2C
+ 0.6V, whichever is
lower. Register bits control the enable for each output pair and a global enable bit (GLOBALEN#) disables all
outputs except the feeback output pair. A low places the disabled output pair in a high impedance state. Outputs
are active during power up and are guaranteed to be at the correct duty cycle and period after the clock
stabilization time.
General Description (Continued)
Device I2C address = 11001, A1, A0, R/W
I
2
C Table: Output Control Register
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLK0EN
CLK1EN
CLK2EN
CLK3EN
CLK4EN
CLK5EN
CLK6EN
CLK7EN
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
I
2
C Table: Output Control Register
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
Reserved
Output Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLK8EN
CLK9EN
CLK10EN
CLK11EN
CLK12EN
Reserved
Reserved
GLOBALEN#
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
0
0
0
NOTE: GLOBALEN# does not tristate the feedback output pair. The PLL continues to run and maintains lock even though all other outputs are tri-stated
Disable = Output in high-impedance state
Enable
Enable
0
1
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
Disable
Disable
A6,A7
A8,A9
B11,C11
D11,E11
F11,G11
PWD
A2,A3
A4,A5
Byte 0
Pin #
Name
Type
Disable
Disable
H11,J11
Byte 1
Pin #
PWD
L8,L9
L6,L7
L4,L5
L2,L3
H1,J1
-
-
Disable
Disable
Disable
Disable
Disable
-
-
Enable
Enable
Enable
Enable
Enable
-
-
Name
Type
0
1
-
Enable
Disable
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| ICS95V860YHLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
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