ICS95V850 0458G—11/21/08 General Layout Precautions: Use copper flooded ground on the top signal layer under the clock buffer The area under U1 " />
參數資料
型號: ICS95V850AG
廠商: IDT, Integrated Device Technology Inc
文件頁數: 10/10頁
文件大小: 0K
描述: IC CLK DVR PLL 1:10 48TSSOP
產品變化通告: Product Discontinuation 09/Dec/2011
標準包裝: 39
類型: 時鐘緩沖器/驅動器,多路復用器
PLL:
主要目的: 存儲器,DDR
輸入: LVCMOS,LVDS,LVPELL,LVTTL
輸出: SSTL-2
電路數: 1
比率 - 輸入:輸出: 1:10
差分 - 輸入:輸出: 是/是
頻率 - 最大: 210MHz
電源電壓: 2.3 V ~ 2.7 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應商設備封裝: 48-TSSOP
包裝: 管件
其它名稱: 95V850AG
9
ICS95V850
0458G—11/21/08
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1)
Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2)
Make all power and ground traces are as wide as the via
pad for lower inductance.
3)
VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4)
Notice that ground vias are never shared.
5)
When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6)
Differential mode clock output traces are routed:
a.
With a ground trace between the pairs. Trace is
grounded on both ends.
b.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
7) Terminate differential CLK_IN and FB_IN traces after
routing to buffer pads.
Component Values:
Ref Desg.
Value
Description
Package
C1,C4,C5,
C7,C11,C12
.01uF
CERAMIC MLC
0603
C2,C3,C8,
C9
4.7uF
CERAMIC MLC
1206
C10
.22uF
CERAMIC MLC
0603
C6
2200pF
CERAMIC MLC
0603
R9,R12
120
0603
R9
4.7
0603
U1
ICS95V850
TSSOP48
Recommended Layout for the ICS95V850
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