參數(shù)資料
型號(hào): ICS954321YG-T
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁(yè)數(shù): 4/18頁(yè)
文件大小: 221K
代理商: ICS954321YG-T
12
Integrated
Circuit
Systems, Inc.
ICS954321
1078A—08/02/05
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Core Supply Voltage
VDD_A
-
VDD + 0.5V
V
1
3.3V Logic Input Supply
Voltage
VDD_In
-
GND - 0.5
VDD + 0.5V
V
1
Storage Temperature
Ts
-
-65
150
°C
1
Ambient Operating Temp
Tambient
-
070
°C
1
Case Temperature
Tcase
-
115
°C
1
Input ESD protection HBM
ESD prot
-
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V1
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Low Threshold Input-
High Voltage
VIH_FS
3.3 V +/-5%
0.7
VDD + 0.3
V1
Low Threshold Input-
Low Voltage
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
1
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
350
mA
1
Operating Current
IDD3.3OP
all outputs driven
400
mA
1
all diff pairs driven
70
mA
1
all differential pairs tri-stated
12
mA
1
Input Frequency
Fi
VDD = 3.3 V
14.31818
MHz
2
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up or de-
assertion of PD to 1st clock
1.8
ms
1
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_PD
CPU output enable after
PD de-assertion
300
us
1
Tfall_PD
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
VDD
2.7
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at
VOL = 0.4 V
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input Low Current
Powerdown Current
IDD3.3PD
Input Capacitance
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