參數(shù)資料
型號(hào)： ICS952621YGLF-T
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 6.10 MM, 0.50 MM PITCH, LEAD FREE, MO-153, TSSOP-48
文件頁(yè)數(shù)： 4/17頁(yè)
文件大?。?/td> 155K
代理商： ICS952621YGLF-T
12
Integrated
Circuit
Systems, Inc.
ICS952621
0756C—04/19/05
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PD#, Power Down
#
N
W
D
R
W
PU
P
C#
U
P
CC
R
S#
C
R
S6
6
V
3I
C
P
/
F
I
C
PT
O
D
/
B
S
UF
E
Re
t
o
N
1l
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nz
H
M
6
6z
H
M
3
3z
H
M
8
4z
H
M
8
1
3
.
4
1
0r
o
2
*
f
e
r
I
t
a
o
l
F
t
a
o
l
F2
*
f
e
r
I
t
a
o
l
F
r
o
t
a
o
l
Fw
o
Lw
o
Lw
o
Lw
o
L
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will the
tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
PD# Assertion
相關(guān)PDF資料
PDF描述
ICS952623YGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS952624YFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952702YFLFT 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952702YFT 222 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS952703YFLFT 217.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS952623 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952623YFT 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952623YGT 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952702 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for K7 System
ICS952702YFLF-T 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for K7 System
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*