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參數(shù)資料
| 型號： | ICS952621 |
| 英文描述： | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| 中文描述： | 可編程定時控制中心⑩處理器的下一代?、?/td> |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ICS952621 |
4
Integrated
Circuit
Systems, Inc.
ICS952621
0756A—09/10/04
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
Parameter
Min
Max
Units
V
V
°C
°C
°C
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
V
DD +
0.5V
V
DD +
0.5V
150
70
115
-0.5
-65
0
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
V
IH
3.3V +/-5%
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
3.3V +/-5%
V
SS
-
0.3
-5
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
uA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
V
IN
= 0 V; Inputs with pull-up
resistors
-5
uA
I
IL2
-200
uA
Operating Supply Current
I
DD3.3OP
Full Active, C
L
= Full load;
260
0.3
350
mA
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
35
12
mA
mA
MHz
nH
pF
pF
pF
Input Frequency
3
Pin Inductance
1
F
i
L
pin
C
IN
C
OUT
C
INX
14.31818
3
1
1
1
1
7
5
6
5
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-
assertion of PD# to 1st clock.
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Clk Stabilization
1,2
T
STAB
1.8
ms
1,2
Modulation Frequency
30
33
kHz
1
Tdrive_PD#
300
us
1
Tfall_Pd#
Trise_Pd#
5
5
ns
ns
1
2
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
I
DD3.3PD
Input Capacitance
1
Input Low Current
Powerdown Current
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