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參數(shù)資料
| 型號： | ICS952607 |
| 英文描述： | 16-Bit Buffers/Drivers With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 可編程定時控制中心，為下一代P4處理器 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 214K |
| 代理商： | ICS952607 |
18
Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
0734—07/16/04
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3V +/-5%; C
L
=2pF
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Current Source Output
Impedance
Zo
1
V
O
= V
x
3000
1
Voltage High
VHigh
660
850
1
Voltage Low
VLow
-150
150
1
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
1150
1
1
1
-300
250
Vcross(abs)
550
mV
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
see Tperiod min-max values
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
140
mV
1
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
t
r
t
f
d-t
r
d-t
f
-300
175
175
300
700
700
125
125
ppm
ps
ps
ps
ps
1,2
1
1
1
1
Duty Cycle
d
t3
Measurement from differential
wavefrom
V
T
= 50%
Measurement from differential
wavefrom
45
55
%
1
Skew
t
sk3
100
ps
1
Jitter, Cycle to cycle
t
jcyc-cyc
125
ps
1
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
Statistical measurement on
single ended signal using
oscilloscope math function.
mV
Measurement on single ended
signal using absolute value.
mV
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