參數(shù)資料
型號(hào): ICS952606
英文描述: Programmable Timing Control Hub for Next Gen P4 processor
中文描述: 可編程定時(shí)控制中心,為下一代P4處理器
文件頁(yè)數(shù): 14/20頁(yè)
文件大?。?/td> 162K
代理商: ICS952606
14
Integrated
Circuit
Systems, Inc.
ICS952606
0717F—06/10/05
I
2
C Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
I
2
C Table: Reserved
Byte 9
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
-
-
-
-
-
-
-
-
0
1
PWD
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
I
2
C Table: Reserved
Byte 10
Pin #
Name
Control Function
M/N prog Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
-
-
-
-
-
-
-
-
0
1
PWD
0
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M/N prog Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Disable
Enable
I
2
C Table: VCO Frequency Control Register
Pin #
Bit 7
-
Name
N Div8
Control Function
N Divider Bit 8
The decimal
representation of M Div
(6:0) is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Type
RW
0
-
1
-
PWD
X
Bit 6
M Div6
RW
-
-
X
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
RESERVED
-
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
-
-
-
-
-
-
Byte 8
-
Byte 11
-
-
Writing to this register
will configure how
many bytes will be read
back, default is 08
= 8
bytes.
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