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參數(shù)資料
| 型號(hào)： | ICS952001YGT |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | ICS952001YGT |
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11
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
mA
Operating
IDD3.3OP
CL = 30 pF; CPU @ 133 MHz
280
mA
Supply Current
Power Down
IDD3.3PD
CL = 0 pF
25
mA
Supply Current
Input frequency
Fi
VDD = 3.3 V
14.32
MHz
Pin Inductance
Lpin
7nH
Input Capacitance
1
CIN
Logic Inputs
5
pF
Cout
Out put pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition Time
1
Ttrans
To 1st crossing of target Freq.
3
mS
Settling Time
1
Ts
From 1st crossing to 1% target Freq.
3
mS
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target Freq.
3
mS
Delay
tPZH,tPZH
output enable delay (all outputs)
1
10
nS
tPLZ,tPZH
output disable delay (all outputs)
1
10
nS
1Guaranteed by design, not 100% tested in production.
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