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參數(shù)資料
| 型號(hào)： | ICS952001 |
| 英文描述： | Preliminary Product Previes |
| 中文描述： | 初步產(chǎn)品Previes |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 212K |
| 代理商： | ICS952001 |
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Pin Description
The
ICS952001
is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The
ICS952001
is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
PIN NUMBER
1, 11, 13, 19, 29,
42, 48
PIN NAME
TYPE
DESCRIPTION
VDD
PWR
Power supply for 3.3V
FS0
REF0
FS1
REF1
FS2
REF2
IN
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
OUT
IN
OUT
IN
OUT
5, 8, 18, 24, 25,
32, 37, 41, 46
6
7
10, 9
GND
PWR
Ground pin for 3V outputs.
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Hyperzip clock outputs.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
OUT
OUT
ZCLK(1:0)
12
PCI_STOP#
IN
FS3
IN
PCICLK_F0
FS4
PCICLK_F1
OUT
IN
OUT
23, 22, 21, 20, 17,
16
PCICLK (5:0)
OUT
PCI clock outputs.
MULTISEL
24_48MHz
48MHz
AVDD
AGPCLK (1:0)
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Clock output for super I/O/USB default is 24MHz
48MHz output clock
Analog power supply 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
Data pin for I
2
C circuitry 5V tolerant
Clock pin of I
2
C circuitry 5V tolerant
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase
with SDRAM clocks. These open drain outputs need an external 1.5V pull-
up.
Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
SDRAM clock output.
OUT
OUT
PWR
OUT
27
28, 36
30, 31
PD#
IN
Vtt_PWRGD
IN
34
35
SDATA
SCLK
I/O
IN
38
I REF
OUT
43, 39
CPUCLKC (1:0)
OUT
44, 40
CPUCLKT (1:0)
OUT
45
CPU_STOP#
IN
47
SDRAM
OUT
15
26
33
2
3
4
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS952003 | Programmable Timing Control Hub for P4⑩ processor |
| ICS952003YFT | Programmable Timing Control Hub for P4⑩ processor |
| ICS952004 | 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85 |
| ICS952301 | Frequency Timing Generator for Transmeta Systems |
| ICS952302 | Frequency Generator for TransmetaTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS952001AF | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS952001AFLF | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS952001AFLFT | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS952001AFT | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS952003 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Programmable Timing Control Hub? for P4? processor |
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