參數資料
型號: ICS951901yFLF-T
英文描述: Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
中文描述: 可編程頻率發(fā)生器
文件頁數: 2/19頁
文件大?。?/td> 180K
代理商: ICS951901YFLF-T
2
ICS951901
0670B—07/15/04
General Description
Pin Configuration
The
ICS951901
is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.
The
ICS951901
belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
E
1
D
2
O
M
n
7
2
n
8
2
n
0
3
n
1
3
n
0
1
1
M
A
R
D
S
0
1
M
A
R
D
S
9
M
A
R
D
S
8
M
A
R
D
S
1
#
P
O
T
S
_
U
P
C
#
P
O
T
S
_
C
P
#
P
O
T
S
_
M
A
R
D
S
#
D
P
MODE Pin Power Management Control Input
PIN NUMBER
1, 7, 15, 22, 25,
35, 43
PIN NAME
TYPE
DESCRIPTION
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
AGPSEL
REF0
FS3
REF1
IN
OUT
IN
OUT
4, 14, 18, 19, 29,
32, 39, 44
5
6
GND
PWR
Ground pin for 3V outputs.
X1
X2
FS1
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48MHz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode
Clock output for super I/O/USB default is 24MHz
Data pin for I
2
C circuitry 5V tolerant
Clock pin of I
2
C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input is low and MODE pin is in Mobile mode
SDRAM clock output
Stops all CPUCLKs clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
SDRAM clock output
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
PCICLK_F
FS2
PCICLK0
PCICLK (4:1)
AGP (1:0)
FS0
48MHz
13, 12, 11, 10
17, 16,
MODE
IN
24_48MHz
SDATA
SCLK
OUT
I/O
IN
23
24
CPU_STOP#
IN
SDRAM11
OUT
PCI_STOP#
IN
SDRAM10
SDRAM9
OUT
OUT
SDRAM_STOP#
IN
PD#
IN
SDRAM8
OUT
26 33, 34, 36,
37, 38, 40, 41,
42
45, 46, 47
48
SDRAM (12,
7:0)
OUT
SDRAM clock outputs
CPUCLK (2:0)
VDDL
OUT
PWR
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
31
20
2
8
9
21
3
30
27
28
相關PDF資料
PDF描述
ICS952001 Preliminary Product Previes
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ICS952003YFT Programmable Timing Control Hub for P4⑩ processor
ICS952004 16-Bit Buffers/Drivers With 3-State Outputs 48-TSSOP -40 to 85
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