參數(shù)資料
型號: ICS950811yFLFT
英文描述: Frequency Generator with 200MHz Differential CPU Clocks
中文描述: 頻率發(fā)生器200MHz的CPU的時鐘差分
文件頁數(shù): 5/18頁
文件大?。?/td> 302K
代理商: ICS950811YFLFT
5
ICS950811
0482E—08/09/07
Byte 0: Control Register
Byte 1: Control Register
t
B
#
n
P
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B
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D
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2
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4
5
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=
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C
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R
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6
6
=
0
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6
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5
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3
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=
1
,
O
d
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S
=
0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I
2
C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2
C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I
2
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2
C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
e
K
K
K
K
K
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C
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C
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1
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=
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4
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0
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C
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K
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