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參數(shù)資料
| 型號(hào)： | ICS950805YFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-118, SSOP-56 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 180K |
| 代理商： | ICS950805YFLF-T |
7
ICS950805
0649H—02/25/05
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
mA
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
Operating Supply
Current
IDD3.3OP
CL = Full load; Select @ 100 MHz
229
230
360
mA
IDD3.3OP
CL =Full load; Select @ 133 MHz
220
233
360
mA
Powerdown Current
IDD3.3PD
IREF=5 mA
38.1
45
mA
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
36
45
pF
Transition time
1
Ttrans
To 1st crossing of target frequency
3
ms
Settling time
1
Ts
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
1
3
ms
Time to first clock
1
T1C
Time to first clock
1.8
ms
tPZH,tPZL
Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
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