參數(shù)資料
型號: ICS950805G-T
英文描述: Frequency Generator with 200MHz Differential CPU Clocks
中文描述: 頻率發(fā)生器200MHz的CPU的時鐘差分
文件頁數(shù): 17/20頁
文件大?。?/td> 180K
代理商: ICS950805G-T
17
ICS950805
0649H—02/25/05
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks
must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with
a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description
is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
PD# Functionality
#
P
O
T
S
_
U
P
C
T
U
P
C
C
U
P
C
6
6
V
3
T
U
O
_
z
H
M
6
6
F
_
K
K
L
L
C
C
I
I
C
P
P
C
K
L
C
I
C
P
T
O
z
D
H
/
B
M
8
S
4
U
1
l
m
r
N
l
m
r
N
z
H
M
6
6
N
I
z
H
M
6
6
N
I
z
H
M
6
6
N
I
z
H
M
6
6
z
H
M
8
4
0
t
M
*
f
t
o
w
o
L
w
o
L
w
o
L
w
o
L
w
o
L
Power Down Assertion of Waveforms - Buffered Mode
0ns
PD#
CPUT 100MHz
CPUC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCI 33MHz
USB 48MHz
REF 14.318MHz
25ns
50ns
相關(guān)PDF資料
PDF描述
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