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參數(shù)資料
| 型號： | ICS950227YFLFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | ICS950227YFLFT |
7
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
I
2C Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
1
Bit 2
BC2
RW
-
1
Bit 1
BC1
RW
-
1
Bit 0
BC0
RW
-
1
I
2C Table: Watchdog Timer Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RESERVED
RW
-
0
Bit 6
RESERVED
RW
-
0
Bit 5
RESERVED
RW
-
0
Bit 4
WD4
RW
-
0
Bit 3
WD3
RW
-
1
Bit 2
WD2
RW
-
0
Bit 1
WD1
RW
-
1
Bit 0
WD0
RW
-
0
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Bit 6
WDEN
Watchdog Enable
RW
OFF
ON
0
Bit 4
WD SS EN
RW
-
0
Bit 3
WD MultSEL
RW
-
0
Bit 2
WD FS2
RW
-
0
Bit 1
WD FS1
RW
-
0
Bit 0
WD FS0
RW
-
0
I
2C Table: VCO Frequency Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
N Div8
N Divider Bit 8
RW
-
X
Bit 6
M Div6
RW
-
X
Bit 5
M Div5
RW
-
X
Bit 4
M Div4
RW
-
X
Bit 3
M Div3
RW
-
X
Bit 2
M Div2
RW
-
X
Bit 1
M Div1
RW
-
X
Bit 0
M Div0
RW
-
X
The decimal
representation of M Div
(6:0) is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
-
0
-
Writing to these bit will
configure the safe
frequency configuration
-
WD Safe Frequency
Mode
RW
Latched
FS/Byte0
WD B10
b(4:0)
-
Bit 5
-WDFSEN
RW
Latched
Input
IIC Prog.
B(11:17)
0
Bit 7
-M/NEN
M/N Programming
Enable
Type
0
1
PWD
Byte 10
Pin #
Name
Control Function
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is10X 290ms
=2.9seconds
-
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
-
Byte 8
-
Byte 11
Byte 9
-
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