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參數(shù)資料
| 型號： | ICS950220 |
| 英文描述： | Programmable Timing Control Hub⑩ for P4⑩ |
| 中文描述： | 可編程定時控制中心，為小四至⑩⑩ |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 183K |
| 代理商： | ICS950220 |
Integrated
Circuit
Systems, Inc.
ICS950220
0467F—07/28/05
Block Diagram
Pin Configuration
Recommended Application:
CK-408 clock for Intel
845 chipset.
Output Features:
3 - Pairs of differential CPU clocks @ 3.3V
3 - 3V66 @ 3.3V
9 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V, 48MHz, 24Mhz or 66MHz
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Programmable Timing Control Hub for P4
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
48-Pin 300-mil SSOP
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
4
S
F
3
S
F
2
S
F
1
S
F
0
S
F
K
L
z
C
H
U
M
P
C
6
z
6
H
V
3
M
K
L
z
C
H
I
C
M
P
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
3
0
0
3
3
6
6
0
0
2
1
1
7
7
7
7
6
6
6
6
6
6
6
6
3
3
4
3
3
3
3
3
3
3
3
3
7
0
Frequency Table
For additional frequency selections please refer to Byte 0.
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
48MHz_DOT
3V66_0/24_48MHZ#
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
WDEN
SEL24_48
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
PD#
I REF
Control
Logic
Config.
Reg.
REF
3
7
3
3V66 (3:1)
3V66
DIVDER
/2
3
CPUCLKT (2:0)
CPUCLKC (2:0)
Reset#
VDDREF
X1
X2
GND
*FS0/PCICLK7
**FS1/PCICLK8
VDDPCI
GND
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
1
1
1
REF/FS2**
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
GND
48MHz_USB/FS3**
48MHz_DOT/SEL_24_48*
AVDD48
GND
3V66_0/24_48MHZ#/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#*
GND
1
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
9
20
21
22
23
24
48
47
46
45
44
43
42
41
40
3
9
38
37
36
35
34
33
32
31
30
2
9
28
27
26
25
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS950220AFLF | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS950220AFLFT | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS950220YFLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for P4⑩ |
| ICS950220YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for P4⑩ |
| ICS950223 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub? for P4? |
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