參數(shù)資料
型號(hào)： ICS950201YFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, MO-118, SSOP-56
文件頁(yè)數(shù)： 11/16頁(yè)
文件大小： 224K
代理商： ICS950201YFT
4
Integrated
Circuit
Systems, Inc.
ICS950201
0460I—12/09/04
Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I
2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2C Byte 0 Bit3. In Software mode it is not allowed to pull the external
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these
modes.
In Hardware mode the I
2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
off, and external resistor termination will bring CPUCLKC low.
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相關(guān)PDF資料
PDF描述
ICS950201YF-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS950201YGLF-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS950201YFLF-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS950201YGLF-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS950201YG-T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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