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參數(shù)資料
| 型號： | ICS94252YFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 136K |
| 代理商： | ICS94252YFLF-T |
2
ICS94252
0456B—04/12/04
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
3:
Internal Pull-down resistor of 120K to GND on indicated inputs.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1,45
VDDL
PWR
Power supply pins, nominal 2.5V
2
IOAPIC
OUT
2.5V clock outputs
4
X1
IN
Crystal input,nominally 14.318MHz.
5
X2
OUT
Crystal output, nominally 14.318MHz.
3, 11, 16, 23,
29, 34, 41, 48
GND
PWR
Ground pins
6, 8, 17, 21, 28,
35, 40
VDD
PWR
Power supply pins, nominal 3.3V
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 MHz reference clock.
FS1
2, 3
IN
Frequency select pin.
AGP0
OUT
AGP outputs defined as 2X PCI frequency. These may not be
stopped.
10
AGP1
OUT
AGP outputs defined as 2X PCI frequency. These may not be
stopped.
PCICLK_F
OUT
Free running PCICLK not stoped by PCI_STOP#
FS2
1, 3
IN
Frequency select pin.
PCICLK2
OUT
PCI clock output
RESET#
OUT
Real time system reset signal for frequency value or watchdog
timmer timeout. This signal is active low. Output is selectable via I
2C
Byte 5 bit7
19, 14, 13
PCICLK
(4, 1, 0)
OUT
PCI clock outputs.
PCICLK3
OUT
PCI clock output.
MODE
1, 3
IN
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
PD#
1
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms. This pin will be activiated when
PCICLK5
OUT
PCI clock output.
FS3
2, 3
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
24
SCLK
IN
Clock input of I
2C input, 5V tolerant input
PD#
1
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms. This pin will be activiated when
SDRAM12
OUT
SDRAM clock output.
CPU_STOP#
1
IN
This asynchronous input halts CPU, SDRAM, and AGP clocks at
logic "0" level when driven low, the stop selection can be
programmed through I
2C.
SDRAM11
OUT
SDRAM clock output.
PCI_STOP#
1
IN
Stops all PCICLKsbesides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM10
OUT
SDRAM clock output.
30, 31, 32, 33,
36, 37, 38, 39,
42, 43
SDRAM ( 9:0 )
OUT
SDRAM clock outputs.
44
SDATA
IN
Data input for I
2C serial input, 5V tolerant input
46, 47
CPUCLK (1:0)
OUT
2.5V CPU clocks
9
7
27
26
12
25
22
18
20
15
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