參數(shù)資料
型號: ICS94229YF-T
英文描述: Programmable System Clock Chip for AMD - K7 processor
中文描述: 可編程系統(tǒng)時鐘芯片為AMD - k7的處理器
文件頁數(shù): 1/17頁
文件大小: 246K
代理商: ICS94229YF-T
Integrated
Circuit
Systems, Inc.
ICS94229
Third party brands and names are the property of their respective owners.
Block Diagram
94229 Rev - 05/31/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Recommended Application:
VIA KT266 style chipset
Output Features:
1 - Differential pair open drain CPU clocks @ 2.5V
1 - Differential pair push-pull CPU clocks @ 2.5V
11 - PCI including 1 free running and 1 early @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Features:
Programmable output frequency.
Programmable output rise/fall time.
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
Real time system reset output.
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
Skew Specifications:
CPU - CPU: <175ps
PCI - PCI: <500ps
CPU (early - PCI: min=1.0ns, max=2.0ns
CPU cycle to cycle jitter: <250ps
Programmable System Clock Chip for AMD - K7 processor
VDDREF
GND
X1
X2
AVDD48
*FS2/48MHz
*FS3/24_48MHz
GND
*WDEN/PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
SRESET#
REF0/
REF1/FS1*
REF_F
RATIO
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
FS0*
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL24_48#
PLL2
PLL1
Spread
Spectrum
48MHz (1:0)
24_48MHz
PCICLK (8:0)
AGP (2:0)
PCICLK_F
REF_F
PCICLK9_E
SRESET#
RATIO
3
9
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
CPU
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
CPUCLKT0
CPUCLKC0
CPUCLK_CST0
CPUCLK_CSC0
3
S
F
2
S
F
1
S
F
0
S
F
U
)
H
3
3
0
2
0
1
0
0
0
9
0
8
0
7
0
5
0
4
0
2
0
1
6
6
0
0
2
6
6
1
0
0
1
3
3
1
P
C
M
2
2
2
2
1
1
1
1
1
1
1
(
P
)
8
3
0
7
0
0
0
0
0
0
0
7
7
7
7
7
G
H
A
M
7
7
3
7
0
7
6
6
0
7
0
7
0
6
0
7
0
7
0
6
0
6
6
6
6
6
6
6
6
6
6
6
(
K
L
)
8
7
0
3
0
0
0
0
0
0
0
3
3
3
3
3
C
H
I
C
M
(
3
6
3
0
3
3
3
0
3
0
3
0
3
5
3
0
3
0
3
0
3
3
3
3
3
3
3
3
3
3
3
P
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
0
0
0
0
0
0
0
0
0
0
7
0
7
0
3
8
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
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