參數(shù)資料
型號: ICS94203F-T
英文描述: Peripheral IC
中文描述: 外圍芯片
文件頁數(shù): 11/18頁
文件大?。?/td> 183K
代理商: ICS94203F-T
11
ICS94203
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table
1
p
u
o
r
G
z
H
M
6
6
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
0
0
1
M
A
R
D
S
S
t
O
e
n
a
T
t
O
e
n
a
T
O
M
A
R
D
S
o
U
P
C
s
5
s
0
0
5
s
0
s
0
0
5
0
6
6
V
3
o
U
P
C
s
5
s
0
0
5
s
0
s
0
0
5
0
6
6
V
3
o
M
A
R
D
S
s
0
s
0
0
5
s
0
s
0
0
5
0
z
H
M
0
0
1
U
P
C
z
H
n
s
0
s
0
0
s
0
0
5
H
M
M
0
0
a
T
5
5
3
1
3
1
U
A
P
R
C
D
t
s
s
s
z
e
M
z
H
n
s
0
s
0
0
s
0
0
5
H
M
M
3
3
a
T
5
5
3
1
3
1
U
A
P
R
C
D
t
O
5
7
0
7
z
e
M
S
0
s
s
s
5
0
I
C
I
O
P
C
P
D
o
o
&
6
I
6
V
P
S
U
3
s
5
0
y
A
s
0
s
A
/
N
0
5
0
s
5
0
y
A
s
0
s
A
/
N
0
5
0
s
5
0
y
A
s
0
s
A
/
N
0
5
0
s
5
s
0
y
A
5
s
0
s
A
/
N
0
5
0
C
B
s
n
s
n
s
n
T
h
c
h
c
h
c
h
c
n
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70o C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
Input Low Current
I
IL1
V
IN
=0 V;Inputs with no pull-up resistors
Input Low Current
I
IL2
V
IN
=0 V; Inputs with pull-up resistors
Supply Current
I
DD3.3OP100
Power Down
PD
Input frequency
Fi
C
IN
Input Capacitance1
C
IN
C
INX
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
CONDITIONS
MIN
2
V
SS
-0.3
TYP
MAX
V
DD
+0.3
0.8
5
UNITS
V
V
A
uA
uA
mA
mA
MHz
pF
pF
pF
ms
V
IN
= VDD
-5
-200
C
L
=30 pF
346
4.3
14.318
400
600
16
5
5
45
3
V
DD
= 3.3 V;
Logic Inputs
Logic Inputs
X1 & X2 pins
12
27
1
Guaranteed by design, not 100% tested in production.
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