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參數(shù)資料
| 型號(hào)： | ICS93V847AG-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.173 INCH, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 92K |
| 代理商： | ICS93V847AG-T |
Integrated
Circuit
Systems, Inc.
ICS93V847
0611C—06/18/03
Block Diagram
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
Pin Configuration
24-Pin TSSOP
Recommended Applications:
Zero Delay Board Fan Out
Provides complete DDR logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 5 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Switching Characteristics:
Period jitter (>66MHz): <40ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
Functionality
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
AT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
U
O
_
B
F
D
N
GL
H
L
H
L
H
f
o
/
d
e
s
a
p
y
B
D
N
GH
L
H
L
H
L
f
o
/
d
e
s
a
p
y
B
V
5
.
2
)
m
o
n
(
LH
L
H
L
H
n
o
V
5
.
2
)
m
o
n
(
HL
H
L
H
L
n
o
4.40 mm. Body, 0.65 mm. pitch
GND
CLKC0
CLKT0
GND
VDD
CLK_INT
CLK_INC
AVDD
AGND
CLKC1
CLKT1
VDD
CLKT4
CLKC4
CLKC3
CLKT3
VDD
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT2
CLKC2
GND
ICS93V
847
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
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